2 philips semiconductors product speci?cation quad d-type ?ip-?op; positive-edge trigger; 3-state 74hc/hct173 features gated input enable for hold (do nothing) mode gated output enable control edge-triggered d-type register asynchronous master reset output capability: bus driver i cc category: msi general description the 74hc/hct173 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (q 0 to q 3 ) and master reset (mr). when the two data enable inputs ( e 1 and e 2 ) are low, the data on the d n inputs is loaded into the register synchronously with the low-to-high clock (cp) transition. when one or both e n inputs are high one set-up time prior to the low-to-high clock transition, the register will retain the previous data. data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the low-to-high clock transition. the master reset input (mr) is an active high asynchronous input. when mr is high, all four flip-flops are reset (cleared) independently of any other input condition. the 3-state output buffers are controlled by a 2-input nor gate. when both output enable inputs ( oe 1 and oe 2 ) are low, the data in the register is presented to the q n outputs. when one or both oe n inputs are high, the outputs are forced to a high impedance off-state. the 3-state output buffers are completely independent of the register operation; the oe n transition does not affect the clock and reset operations. quick reference data gnd = 0 v; t amb =25 c; t r =t f =6ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay cp to q n mr to q n c l = 15 pf; v cc =5v 17 13 17 17 ns ns f max maximum clock frequency 88 88 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per ?ip-?op notes 1 and 2 20 20 pf
6 philips semiconductors product speci?cation quad d-type ?ip-?op; positive-edge trigger; 3-state 74hc/hct173 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 55 20 16 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.6 t phl propagation delay mr to q n 44 16 13 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.7 t pzh / t pzl 3-state output enable time oe n to q n 52 19 15 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.8 t phz / t plz 3-state output disable time oe n to q n 52 19 15 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.8 t thl / t tlh output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.6 t w clock pulse width high or low 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.6 t w master reset pulse width; high 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.7 t rem removal time mr to cp 60 12 10 - 8 - 3 - 2 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.7 t su set-up time e n to cp 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.9 t su set-up time d n to cp 60 12 10 17 6 5 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.9
7 philips semiconductors product speci?cation quad d-type ?ip-?op; positive-edge trigger; 3-state 74hc/hct173 t h hold time e n to cp 0 0 0 - 17 - 6 - 5 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.9 t h hold time d n to cp 1 1 1 - 11 - 4 - 3 1 1 1 1 1 1 ns 2.0 4.5 6.0 fig.9 f max maximum clock pulse frequency 6.0 30 35 26 80 95 4.8 24 28 4.0 20 24 mhz 2.0 4.5 6.0 fig.6 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
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